Socket FM2+

редактировать
Socket FM2+
TypeµPGA -ZIF
Chip form factorsPGA
Contacts906
PredecessorFM2
SuccessorAM4

This article is part of the CPU socket series
CPU socket for laptop AMD CPUs

Socket FM2+(FM2b, FM2r2) is a CPU socket used by AMD 's desktop "Kaveri" APUs (Steamroller -based) and Godavari APUs (Steamroller -based) to connect to the motherboard. The FM2+ has a slightly different pin configuration to Socket FM2 with two additional pin sockets. Socket FM2+ APUs are not compatible with Socket FM2 motherboards due to the aforementioned additional pins. However, socket FM2 APUs such as "Richland" and "Trinity" are compatible with the FM2+ socket.

  • ECC DIMMs are supported on Socket FP3 but not supported on the Socket FM2+ package. GDDR5 or HBM memory are not supported.
  • There are 3 PCI Express cores: one 2 ×16 core and two 5 ×8 cores. There are 8 configurable ports, which can be divided into 2 groups:
    • Gfx-group: contains 2 ×8 ports. Each port can be limited to lower link widths for applications that require fewer lanes. Additionally, the two ports can be combined to create a single ×16 link.
    • GPP-group: contains 1 ×4 UMI and 5 General Purpose Ports (GPP).

All PCIe links are capable of supporting PCIe 2.x data rates. In addition, the Gfx link is capable of supporting PCIe 3.x data rate.

For available chipsets consult Fusion controller hubs (FCH).

Its mobile counterpart is Socket FP3 (µBGA906).

Heatsink

The 4 holes for fastening the heatsink to the motherboard are placed in a rectangle with lateral lengths of 48 mm and 96 mm for AMD's sockets Socket AM2, Socket AM2+, Socket AM3, Socket AM3+ and Socket FM2. Cooling solutions should therefore be interchangeable.

Feature overview

The following table shows features of AMD 's APUs (see also: List of AMD accelerated processing units ).

[ ] [
  • view
  • talk
]
CodenameServerBasicToronto
MicroKyoto
DesktopMainstreamCarrizo Bristol Ridge Raven Ridge Picasso Renoir
EntryLlano Trinity Richland Kaveri
BasicKabini
MobilePerformanceRenoir
MainstreamLlano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso
EntryDalí
BasicDesna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge
EmbeddedTrinity Bald Eagle Merlin Falcon,. Brown Falcon Great Horned Owl Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,. LX-Family Prairie Falcon Banded Kestrel
PlatformHigh, standard and low powerLow and ultra-low power
ReleasedAug 2011Oct 2012Jun 2013Jan 2014Jun 2015Jun 2016Oct 2017Jan 2019Mar 2020Jan 2011May 2013Apr 2014May 2015Feb 2016Apr 2019
CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+ "Zen Zen+ Zen 2 Bobcat Jaguar Puma Puma+ "Excavator+ "Zen
ISA x86-64 x86-64
Socket DesktopHigh-endN/AN/A
MainstreamN/AAM4
EntryFM1 FM2 FM2+ N/A
BasicN/AN/AAM1 N/A
OtherFS1 FS1+, FP2 FP3 FT1 FT3 FT3b
PCI Express version2.03.02.03.0
Fab. (nm )GF 32SHP. (HKMG SOI )GF 28SHP. (HKMG bulk)GF 14LPP. (FinFET bulk)GF 12LP. (FinFET bulk)TSMC N7. (FinFET bulk)TSMC N40. (bulk)TSMC N28. (HKMG bulk)GF 28SHP. (HKMG bulk)GF 14LPP. (FinFET bulk)
Die area (mm)22824624524525021015675 (+ 28 FCH )107?125149
Min TDP (W)351712104.543.95106
Max APU TDP (W)10095651825
Max stock APU base clock (GHz)33.84.14.13.73.83.63.73.81.752.222.23.23.3
Max APUs per node11
Max CPU cores per APU48242
Max threads per CPU core1212
Integer structure3+32+24+24+2+11+1+1+12+24+2
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHFYesYes
IOMMU N/AYes
BMI1, AES-NI, CLMUL, and F16C N/AYes
MOVBEN/AYes
AVIC, BMI2 and RDRAND N/AYes
ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERON/AYesN/AYes
WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMITN/AYesN/A
FPUs per core 10.5110.51
Pipes per FPU22
FPU pipe width128-bit256-bit80-bit128-bit
CPU instruction set SIMD levelSSE4a AVX AVX2 SSSE3 AVX AVX2
3DNow! 3DNow!+ N/AN/A
PREFETCH/PREFETCHW YesYes
FMA4, LWP, TBM, and XOP N/AYesN/AN/AYesN/A
FMA3 YesYes
L1 data cache per core (KiB)64163232
L1 data cache associativity (ways)2488
L1 instruction caches per core 10.5110.51
Max APU total L1 instruction cache (KiB)2561281922565126412896128
L1 instruction cache associativity (ways)2348234
L2 caches per core 10.5110.51
Max APU total L2 cache (MiB)424121
L2 cache associativity (ways)168168
APU total L3 cache (MiB)N/A48N/A4
APU L3 cache associativity (ways)1616
L3 cache schemeVictim N/AVictimVictim
Max stock DRAM supportDDR3-1866 DDR3-2133 DDR3-2133, DDR4-2400 DDR4-2400 DDR4-2933 DDR4-3200, LPDDR4-4266 DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3-1866, DDR4-2400 DDR4-2400
Max DRAM channels per APU212
Max stock DRAM bandwidth (GB/s) per APU29.86634.13238.40046.93268.25610.66612.80014.93319.20038.400
GPU microarchitecture TeraScale 2 (VLIW5) TeraScale 3 (VLIW4) GCN 2nd gen GCN 3rd gen GCN 5th gen TeraScale 2 (VLIW5) GCN 2nd gen GCN 3rd gen GCN 5th gen
GPU instruction set TeraScale instruction setGCN instruction set TeraScale instruction setGCN instruction set
Max stock GPU base clock (MHz)6008008448661108125014002100538600?8479001200
Max stock GPU base GFLOPS 480614.4648.1886.71134.517601971.22150.486???345.6460.8
3D engineUp to 400:20:8Up to 384:24:6Up to 512:32:8Up to 704:44:16Up to 512:?:?80:8:4128:8:4Up to 192:?:?Up to 192:?:?
IOMMUv1IOMMUv2 IOMMUv1?IOMMUv2
Video decoderUVD 3.0 UVD 4.2 UVD 6.0 VCN 1.0 VCN 2.0 UVD 3.0 UVD 4.0 UVD 4.2 UVD 6.0 UVD 6.3 VCN 1.0
Video encoderN/AVCE 1.0 VCE 2.0 VCE 3.1 N/AVCE 2.0 VCE 3.1
GPU power savingPowerPlay PowerTune PowerPlay PowerTune
TrueAudio N/AYesN/AYes
FreeSync 1. 21. 2
HDCP ?1.41.4. 2.2?1.41.4. 2.2
PlayReady N/A3.0 not yetN/A3.0 not yet
Supported displays 2–32–433 (desktop). 4 (mobile, embedded)4234
/drm/radeonYesN/AYesN/A
/drm/amdgpuN/AYesYesN/AYesYes
External links
Последняя правка сделана 2021-06-08 08:08:54
Содержание доступно по лицензии CC BY-SA 3.0 (если не указано иное).
Обратная связь: support@alphapedia.ru
Соглашение
О проекте