Type | µPGA -ZIF |
---|---|
Chip form factors | PGA |
Contacts | 906 |
Predecessor | FM2 |
Successor | AM4 |
This article is part of the CPU socket series |
Socket FM2+(FM2b, FM2r2) is a CPU socket used by AMD 's desktop "Kaveri" APUs (Steamroller -based) and Godavari APUs (Steamroller -based) to connect to the motherboard. The FM2+ has a slightly different pin configuration to Socket FM2 with two additional pin sockets. Socket FM2+ APUs are not compatible with Socket FM2 motherboards due to the aforementioned additional pins. However, socket FM2 APUs such as "Richland" and "Trinity" are compatible with the FM2+ socket.
All PCIe links are capable of supporting PCIe 2.x data rates. In addition, the Gfx link is capable of supporting PCIe 3.x data rate.
For available chipsets consult Fusion controller hubs (FCH).
Its mobile counterpart is Socket FP3 (µBGA906).
The 4 holes for fastening the heatsink to the motherboard are placed in a rectangle with lateral lengths of 48 mm and 96 mm for AMD's sockets Socket AM2, Socket AM2+, Socket AM3, Socket AM3+ and Socket FM2. Cooling solutions should therefore be interchangeable.
The following table shows features of AMD 's APUs (see also: List of AMD accelerated processing units ).
[ ] [Codename | Server | Basic | Toronto | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Micro | Kyoto | |||||||||||||||||
Desktop | Mainstream | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir | ||||||||||||
Entry | Llano | Trinity | Richland | Kaveri | ||||||||||||||
Basic | Kabini | |||||||||||||||||
Mobile | Performance | Renoir | ||||||||||||||||
Mainstream | Llano | Trinity | Richland | Kaveri | Carrizo | Bristol Ridge | Raven Ridge | Picasso | ||||||||||
Entry | Dalí | |||||||||||||||||
Basic | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge | |||||||||||||
Embedded | Trinity | Bald Eagle | Merlin Falcon,. Brown Falcon | Great Horned Owl | Ontario, Zacate | Kabini | Steppe Eagle, Crowned Eagle,. LX-Family | Prairie Falcon | Banded Kestrel | |||||||||
Platform | High, standard and low power | Low and ultra-low power | ||||||||||||||||
Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019 | |||
CPU microarchitecture | K10 | Piledriver | Steamroller | Excavator | "Excavator+ " | Zen | Zen+ | Zen 2 | Bobcat | Jaguar | Puma | Puma+ | "Excavator+ " | Zen | ||||
ISA | x86-64 | x86-64 | ||||||||||||||||
Socket | Desktop | High-end | N/A | N/A | ||||||||||||||
Mainstream | N/A | AM4 | ||||||||||||||||
Entry | FM1 | FM2 | FM2+ | N/A | ||||||||||||||
Basic | N/A | N/A | AM1 | N/A | ||||||||||||||
Other | FS1 | FS1+, FP2 | FP3 | FT1 | FT3 | FT3b | ||||||||||||
PCI Express version | 2.0 | 3.0 | 2.0 | 3.0 | ||||||||||||||
Fab. (nm ) | GF 32SHP. (HKMG SOI ) | GF 28SHP. (HKMG bulk) | GF 14LPP. (FinFET bulk) | GF 12LP. (FinFET bulk) | TSMC N7. (FinFET bulk) | TSMC N40. (bulk) | TSMC N28. (HKMG bulk) | GF 28SHP. (HKMG bulk) | GF 14LPP. (FinFET bulk) | |||||||||
Die area (mm) | 228 | 246 | 245 | 245 | 250 | 210 | 156 | 75 (+ 28 FCH ) | 107 | ? | 125 | 149 | ||||||
Min TDP (W) | 35 | 17 | 12 | 10 | 4.5 | 4 | 3.95 | 10 | 6 | |||||||||
Max APU TDP (W) | 100 | 95 | 65 | 18 | 25 | |||||||||||||
Max stock APU base clock (GHz) | 3 | 3.8 | 4.1 | 4.1 | 3.7 | 3.8 | 3.6 | 3.7 | 3.8 | 1.75 | 2.2 | 2 | 2.2 | 3.2 | 3.3 | |||
Max APUs per node | 1 | 1 | ||||||||||||||||
Max CPU cores per APU | 4 | 8 | 2 | 4 | 2 | |||||||||||||
Max threads per CPU core | 1 | 2 | 1 | 2 | ||||||||||||||
Integer structure | 3+3 | 2+2 | 4+2 | 4+2+1 | 1+1+1+1 | 2+2 | 4+2 | |||||||||||
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | ||||||||||||||||||
IOMMU | N/A | |||||||||||||||||
BMI1, AES-NI, CLMUL, and F16C | N/A | |||||||||||||||||
MOVBE | N/A | |||||||||||||||||
AVIC, BMI2 and RDRAND | N/A | |||||||||||||||||
ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO | N/A | N/A | ||||||||||||||||
WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT | N/A | N/A | ||||||||||||||||
FPUs per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||
Pipes per FPU | 2 | 2 | ||||||||||||||||
FPU pipe width | 128-bit | 256-bit | 80-bit | 128-bit | ||||||||||||||
CPU instruction set SIMD level | SSE4a | AVX | AVX2 | SSSE3 | AVX | AVX2 | ||||||||||||
3DNow! | 3DNow!+ | N/A | N/A | |||||||||||||||
PREFETCH/PREFETCHW | ||||||||||||||||||
FMA4, LWP, TBM, and XOP | N/A | N/A | N/A | N/A | ||||||||||||||
FMA3 | ||||||||||||||||||
L1 data cache per core (KiB) | 64 | 16 | 32 | 32 | ||||||||||||||
L1 data cache associativity (ways) | 2 | 4 | 8 | 8 | ||||||||||||||
L1 instruction caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||
Max APU total L1 instruction cache (KiB) | 256 | 128 | 192 | 256 | 512 | 64 | 128 | 96 | 128 | |||||||||
L1 instruction cache associativity (ways) | 2 | 3 | 4 | 8 | 2 | 3 | 4 | |||||||||||
L2 caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||
Max APU total L2 cache (MiB) | 4 | 2 | 4 | 1 | 2 | 1 | ||||||||||||
L2 cache associativity (ways) | 16 | 8 | 16 | 8 | ||||||||||||||
APU total L3 cache (MiB) | N/A | 4 | 8 | N/A | 4 | |||||||||||||
APU L3 cache associativity (ways) | 16 | 16 | ||||||||||||||||
L3 cache scheme | Victim | N/A | Victim | Victim | ||||||||||||||
Max stock DRAM support | DDR3-1866 | DDR3-2133 | DDR3-2133, DDR4-2400 | DDR4-2400 | DDR4-2933 | DDR4-3200, LPDDR4-4266 | DDR3L-1333 | DDR3L-1600 | DDR3L-1866 | DDR3-1866, DDR4-2400 | DDR4-2400 | |||||||
Max DRAM channels per APU | 2 | 1 | 2 | |||||||||||||||
Max stock DRAM bandwidth (GB/s) per APU | 29.866 | 34.132 | 38.400 | 46.932 | 68.256 | 10.666 | 12.800 | 14.933 | 19.200 | 38.400 | ||||||||
GPU microarchitecture | TeraScale 2 (VLIW5) | TeraScale 3 (VLIW4) | GCN 2nd gen | GCN 3rd gen | GCN 5th gen | TeraScale 2 (VLIW5) | GCN 2nd gen | GCN 3rd gen | GCN 5th gen | |||||||||
GPU instruction set | TeraScale instruction set | GCN instruction set | TeraScale instruction set | GCN instruction set | ||||||||||||||
Max stock GPU base clock (MHz) | 600 | 800 | 844 | 866 | 1108 | 1250 | 1400 | 2100 | 538 | 600 | ? | 847 | 900 | 1200 | ||||
Max stock GPU base GFLOPS | 480 | 614.4 | 648.1 | 886.7 | 1134.5 | 1760 | 1971.2 | 2150.4 | 86 | ? | ? | ? | 345.6 | 460.8 | ||||
3D engine | Up to 400:20:8 | Up to 384:24:6 | Up to 512:32:8 | Up to 704:44:16 | Up to 512:?:? | 80:8:4 | 128:8:4 | Up to 192:?:? | Up to 192:?:? | |||||||||
IOMMUv1 | IOMMUv2 | IOMMUv1 | ? | IOMMUv2 | ||||||||||||||
Video decoder | UVD 3.0 | UVD 4.2 | UVD 6.0 | VCN 1.0 | VCN 2.0 | UVD 3.0 | UVD 4.0 | UVD 4.2 | UVD 6.0 | UVD 6.3 | VCN 1.0 | |||||||
Video encoder | N/A | VCE 1.0 | VCE 2.0 | VCE 3.1 | N/A | VCE 2.0 | VCE 3.1 | |||||||||||
GPU power saving | PowerPlay | PowerTune | PowerPlay | PowerTune | ||||||||||||||
TrueAudio | N/A | N/A | ||||||||||||||||
FreeSync | 1. 2 | 1. 2 | ||||||||||||||||
HDCP | ? | 1.4 | 1.4. 2.2 | ? | 1.4 | 1.4. 2.2 | ||||||||||||
PlayReady | N/A | 3.0 not yet | N/A | 3.0 not yet | ||||||||||||||
Supported displays | 2–3 | 2–4 | 3 | 3 (desktop). 4 (mobile, embedded) | 4 | 2 | 3 | 4 | ||||||||||
/drm/radeon | N/A | N/A | ||||||||||||||||
/drm/amdgpu | N/A | N/A |